1. Field of the Prior Art
This invention relates to digital signal processing.
2. Description of the Prior Art
Digital signal processing devices, such as digital filters, are used to perform signal processing operations on digital representations of sampled analogue signals such as audio signals. A typical application of such a device for use with a digital audio signal is to provide a frequency-dependent gain adjustment, such as a low-pass, band-pass or high-pass filtering operation.
FIG. 1 is a schematic diagram of a previously proposed digital filtering apparatus in which the characteristics (e.g. frequency response or gain) of a digital filter are dependent on the position of a user-operated control, such as a potentiometer. The apparatus of FIG. 1 may form part of, for example, a digital audio mixing console.
In FIG. 1, the analogue position of a potentiometer 10 is detected by a position encoder 20. The position encoder 20 generates a digital position signal 25 representing the position of the potentiometer 10 at regular intervals determined by clock pulses of a sampling clock signal 28. The digital position signal 25 is then passed to a coefficient generator 30 which produces successive sets of filter coefficients 35 (to be convolved with samples of a digital audio signal) in dependence on the current value of the digital position signal 25. Similar position sampling operations are performed in parallel by further position encoders (e.g. an encoder 21) based on the positions of further potentiometers (e.g. a potentiometer 11).
In order to produce the required filter coefficients, the coefficient generator 30 is programmed with data representing the function assigned to the potentiometer 10. For example, the potentiometer 10 may be a simple "gain" control, in which case the coefficient generator 30 generates a set of coefficients 35 which map an increment or decrement in the digital position signal 25 onto a corresponding increment or decrement in the gain of a digital filter using those coefficients 35. The coefficient generator 30 generates a new set of coefficients 35 at regular intervals, being synchronised by clock pulses of a coefficient update clock 38.
In the example shown in FIG. 1, the coefficient generator in fact generates more than one set of coefficients at a time, with each set of coefficients (e.g. a set 36) corresponding to the output of a respective position encoder.
The successive sets of coefficients 35 are supplied to a signal processor 40 which receives an input digital audio signal 42 (e.g. a 44.1 kilohertz or 48 kilohertz 16 bit digital audio signal) and, using the current set of coefficients 35, generates an output filtered digital audio signal 44. For reasons which will be explained below, some of the coefficients 35 are delayed within the signal processor 40 by a delay element 46. The signal processor also receives the further sets of coefficients 36 etc, and performs further processing of the input digital audio signal 42 using those sets of coefficients.
FIG. 2 is a schematic diagram illustrating the operation of the signal processor 40 of FIG. 1.
The signal processor 40 is a pipelined processing device. This means that the signal processor 40 receives a sample of the input digital audio signal 42 in each sample period of the digital audio signal and supplies an output sample of the output digital audio signal 44 at each sample period. However, the processing required to generate an output sample is performed over the course of more than one sample period. This pipelined arrangement is represented schematically in FIG. 2, in which time is represented along the horizontal axis and a number of discrete processing streams within the signal processor 40 (e.g. separate central processing units or CPUs operating in parallel) are represented on the vertical axis.
In FIG. 2 the processing applied to a particular input sample (sample "n") is represented by shaded portions 50, 52 and 54. When sample n is received by the signal processor 40, it is initially processed at various times during a first sample period in a subset of the processing streams represented by the shaded portion 50. In the following sample period the processing of sample n is represented by the shaded portions 52 (the portion 50' in the second sample period illustrated being used to process the next sample n+1). Finally, in the third sample period illustrated in FIG. 2, the processing continues as represented by a shaded portion 54, before the filtered sample n is output by the signal processor 40.
FIG. 3 is a schematic diagram of an infinite impulse response (IIR) digital filter which may be embodied in the signal processor 40. This type of filter is conventional and is described in, for example, the book "Digital Signal Processing" (Proakis and Manolakis, MacMillan Publishing Company, 1992). In this type of filter, an input signal is delayed by successive delay elements (Z.sup.-1) with the output of various "taps" in the change of delay elements being multiplied by respective filter coefficients c1-c5. The results of the multiplication stages are summed by an adder 60 to generate the filtered output signal.
When a filter of the type illustrated in FIG. 3 is implemented in a pipelined signal processor 40 of the type described above, constraints on the number of processing operations which can be performed during a single sample period often mean that it is impossible to schedule all of the multiply operations used in the generation of a single filtered output sample (i.e. using a single set of coefficients such as the set 35) to take place during the same sample period. This situation is illustrated in FIG. 4, which is a further schematic timing diagram illustrating the operation of the signal processor 40 of FIG. 1.
In FIG. 4, the five multiply operations required to implement the filter of FIG. 3 are split between two successive sample periods 70, 72. In particular, the multiply operations for coefficients c1-c3 of a particular coefficient set are implemented in the sample period 70 and the multiply operations for the coefficients c4 and c5 of that same coefficient set are implemented in the sample period 72.
When the filter response has to be changed (e.g. because the potentiometer 10 has been moved by the user), it is important that all of the filter coefficients c1 to c5 are changed for effectively the same output audio sample, so that the situation does not arise that half of a filtering operation is carried out using one version of a particular set of coefficients and half using an updated version of that set. However, the coefficient generator 30 generates a complete set of coefficients 35 in parallel and at the same time, so this has meant that in the previously proposed apparatus of FIG. 1 a subset of the coefficients has to be delayed so that a particular filtering operation can be completed using a single version of the set of coefficients 35.
In FIG. 4, this situation is illustrated schematically in that a clock pulse (CU) of the coefficient update clock 38 occurs between the sample period 70 and the sample period 72. This means that the current set of coefficients 35 output by the coefficient generator 30 during the sample period 70 is, say, coefficient set (version) n and the set of coefficients output during the sample period 72 is, say, a different coefficient set (version) n+1. The multiplications by coefficients c1 to c3 take place using the coefficient set n during the sample period 70. However, in order that the remaining multiplications (by c4 and c5) are performed using coefficient set n rather than coefficient set n+1, the coefficients c4 and c5 have to be delayed during the sample period 70 for use during the sample period 72.
The situation described above, in which the coefficient generator 30 generates a plurality of complete sets of coefficients 35, 36 together and in parallel but some of those coefficients have to be delayed by the signal processor 40 for use in subsequent sample periods, is wasteful of the available processing resources because (a) the coefficient generator 30 is working needlessly fast, and (b) the implementation of the delay within the signal processor occupies a part of the limited processing and memory resources of the signal processor 40.